1. Field
Exemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to a semiconductor memory device and a method for operating the same.
2. Description of the Related Art
Generally, semiconductor memory devices are divided into volatile memory devices, such as Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM), and non-volatile memory devices, such as Programmable Read Only Memory (PROM), Erasable PROM (EPROM), Electrically EPROM (EEPROM), and flash memory device. What distinguishes a non-volatile memory device from a volatile memory device is whether or not the data stored in a memory cell is retained after a certain time.
In other words, whereas the volatile memory device does not retain the data stored in its memory cells after the certain time, the non-volatile memory device retains the data stored in its memory cells after the certain time. Therefore, the volatile memory device necessarily performs an additional operation such as a refresh operation to retain the data, whereas the non-volatile memory device does not perform the refresh operation. Since this feature of the non-volatile memory device is appropriate for low power consumption and high integration, the non-volatile memory device has been widely used as a storage medium for portable devices in recent years.
Among the non volatile memory devices, a flash memory device stores a data in a memory cell through a program operation and an erase operation. The program operation means an operation for accumulating electrons in a floating gate of a transistor that constitutes a memory cell, and the erase operation means an operation for discharging the electrons that are accumulated in the floating gate of the transistor into a substrate. The flash memory device accumulates or discharges electrons in or out of the floating gate through the program operation or the erase operation, and each memory cell gets a cell distribution corresponding to a data of ‘0’ or ‘1’.
As described above, one memory cell stores a data of ‘0’ or ‘1’. In other words, one memory cell stores a one-bit data, and such memory cell is referred to as a single-level cell. Recently, a method of storing a data of more than one bit in one memory cell has been developed, and this kind of a memory cell is referred to as a multi-level cell. The single-level cell needs one read reference voltage to decide whether the data stored in the memory cell is ‘0’ or ‘1’. On the other hand, the multi-level cell, for example, a two-level cell needs at least three read reference voltages to decide whether the data stored in the memory cell is ‘00’, ‘01’, ‘10’, or ‘11’.
FIG. 1 is a cell distribution diagram illustrating a program operation of a conventional flash memory device. Referring to FIG. 1, (A) shows a cell distribution during a lower-bit program operation. For example, a distribution ‘E’ is the distribution of the erased cells in which data ‘1’ is stored, and a distribution ‘PV1’ is the distribution of the programmed cells in which data ‘0’ is stored. Meanwhile, (B) shows a cell distribution during an upper-bit program operation. For example, a distribution ‘E’ is the distribution of the erased cells in which data ‘11’ is stored; a distribution ‘01’ is the distribution of the programmed cells in which data ‘01’ is stored; a distribution ‘PV2’ is also the distribution of the programmed cells in which data ‘10’ is stored; and a distribution ‘PV 3’ is also the distribution of the programmed cells in which data ‘00’ is stored.
To be specific, two distributions are formed in a lower-bit page of the memory cell through the lower-bit program operation (A), and it takes one reference voltage VR to distinguish the two distributions from each other. Four distributions are formed in an upper-bit page of the memory cell through the upper-bit program operation (B), and it takes three reference voltages, which are first to third reference voltages VR1, VR2 and VR3 to distinguish the four distributions from each other.
Meanwhile, a flash memory device loses data for various reasons. Among the reasons is a case that there is an abnormality in power in the course of performing an upper-bit program operation after completing a lower-bit program operation and forming a normal cell distribution. When the abnormality in power occurs, not only a cell distribution that is supposed to be formed through the upper-bit program operation but also the cell distribution before the upper-bit program operation, which is the cell distribution that is normally formed through the lower-bit program operation, is lost. Therefore, the reliability of a flash memory device is declined due to such data loss.